1/13 I've been looking at intel's web site and can't find any sort of
white paper on design principles that make the CPU keep up with
moore's law. I heard that things like the main components of
performance is memory and manufacturing process. The fancy stuff
like pipelining hyperthreading etc, doesn't really do much. The
amount of onboard cache memory is still the determining factor in
performance. And that is tied to the manufacturing process. It has
been a while since I took CS152. Is this still true? Most of the
advances in microprocessor design is in integrating bigger and bigger
cache into the chip?
\_ Making transistors smaller also helps. Smaller devices run faster
than larger ones since both the resistance and the capacitance
depend on the device size.
\_ given practical limits on size and cost of a die, more cache
implies process improvement. the pa guys used to do offchip
sram in a mcm, but i think they've given up on that also (because
at the end of the day the interconnect between cpu and sram is
slow). (of course i've not looked at general purpose cpu's
for many years so i may be wrong). intel's claim of everything
being essentially only memory and cache bandwidth limited
may be true for the class of cpu's they mostly build (general
purpose) and the class of problems they solve (large grained),
but certainly is not true for all architectures and all
applications. also i guess depends on the definition of a cpu.
e.g. just as the bandwidth of a truck full of mag tapes is
stunning, so is the computational power of a die full of small
(friend of mine makes a 27k gate one) processors.
so in general they are wrong, though they are probably
correct specifically for the problem they are trying to solve.
\_ well, my wrong is probably too strong, because it's always
memory and cache bandwidth, but it's certainly not the only
thing.
\_ Moore's law specifies #transistors/chip. The fabrication process
allows features to shrink roughly in line with ML. Lately, issues
like scaling (wires scale differently than transistors) and routing
(connecting the transistors to each other) are tougher than shrinking
transistors.
\_ nothing lately about it. i took cs250 15 years ago, and it
was obvious to me then that routing was the problem. power
is a much more interesting and recent problem.
\_ When I worked developing CAD tools @ Intel 1997-2000, those
were the emerging problems. Hence, lately. -emarkp
\_ back in the day when i banged sea-of-gates chips late
80's and early 90's, it was as simple as throwing the
netlist over the wall to the backend guys. 93-ish
we started having to worry about floorplanning, and
95 i started doing cot and p&r was a problem. which is
not to say that p&r was not a problem earlier, as anyone
who pushed polygons by hand will tell you (which is what
i referred to when i mentioned c250 above), rather
that around that time density and technology made the
problem much less tractable. you also have to understand
that intel does not have the most normal design flow, and
your experience at intel probably does not reflect
industry experience in general. |
http://csua.com/feed/