Entry 25391 (Berkeley CSUA MOTD)

Berkeley CSUA MOTD:Entry 25391

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2026/07/27 [General] UID:1000 Activity:popular

7/27

2002/7/19-20 [Computer/HW/Languages] UID:25391 Activity:high

7/19    Can somebody recommend a book (or a web site) that has step by step
        descriptions of how an ASIC is built?  From the verilog/vhdl to
        actual silicon.  What tools are used and what happens at every
        stage, etc.  Thanks.
        \_ If you're still in school, take 141 or 152 or intern at an ASIC
           design group. If you're out in the job market, join one.
           Unfortunately, ASIC design is not something easily done "on
           your own" as is with software where you can just write your
           own stuff or download the Linux/BSD source and muck around
           with. Many of the tools like VCS and DC have very expensive
           license fees. Learning Verilog or VHDL isn't that hard. Just
           pick up an HDL book (I'll look up the one I use) and try it
           on a free simulator like Icarus. But learning an HDL is kind
           of trivial and only a tiny portion of the entire ASIC design
           flow. For more HDL info, try going to
           http://home.europa.com/~celiac/othersite.html
           \_ The book my co-workers use is Verilog HDL by Palnitkar.
              Like K&R, it's a crappy read but a decent reference.
           \_ I took 152 ten years ago and it didn't tell me how an ASIC is
              built.  --- !OP
              \_ Well, he/she wanted to gain experience using an HDL and
                 152 made you use VHDL, at least.
                 \_ there's a difference between HDL and synthesizable HDL
        \_ I'm not an ASIC guy but all the ASIC guys I know say it's *very*
           boring work.  What's your interest in the topic?
           \_ really?  architecture and microarchitecture is fun.  so is
              coding.  simulation and bug-fixing is fun, tho i find test
              writing moderately boring.  i like hacking synthesis stuff,
              but then i'm an old fart.  back end is mostly boring, tho
              there are some interesting bits as i look more into it.  lab
              bring up is highly amusing, tho i've noticed that other people
              don't seem to share my enthusiasm.
              \_ dunno.  like I said I'm not an ASIC guy.  I know nothing about
                 it.  I was mostly curious as to what the OP saw in it that my
                 ASIC buddies don't.
        \_ http://parts.jpl.nasa.gov/asic/sect.1.1.html
        \_ sjmercury, 1/31/2002.  there's a 3/4 page graphic on page 4c of
           the business section that explains all the steps from arch to
           bring up to system integration.

2026/07/27 [General] UID:1000 Activity:popular

7/27

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