Berkeley CSUA MOTD:Entry 24564
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2025/05/24 [General] UID:1000 Activity:popular
5/24    

2002/4/24 [Computer/HW/CPU] UID:24564 Activity:nil
4/23    http://www.theregister.co.uk/content/53/24973.html
        Nick Weaver now officially almost famous.
        \_ Nick Weaver and/or the article author needs to take e190.
2025/05/24 [General] UID:1000 Activity:popular
5/24    

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Cache (1692 bytes)
www.theregister.co.uk/content/53/24973.html -> www.theregister.co.uk/2002/04/23/itanic_its_all_academic_now/
Itanic: It's all academic now - Official By 40 Andrew Orlowski in San Francisco Published Tuesday 23rd April 2002 08:47 GMT The name Itanic, coined here several years ago by Mike Magee, for Intel's IA-64 processor has been formally adopted by academia. Nick Weaver, a 28-year old graduate student and researcher, teaches computer science classes at the University of California's Berkeley school, and as you can see from his 41 "special topics" class, week 16 next month will be devoted to the "Voyage of the Itanic". We invited him to elaborate: "The first good idea was one they explored several years ago in a paper from HP. Transmeta gets around this by always recompiling, and it's not a problem in the DSP community. But it is a problem if you want to do a 'general purpose' processor" Nick commends deferred exception handling and low-cost checkpointing as two "beautiful features" of the IA-64 architecture. They make this very nice by propagating error conditions. The register window also incurs a performance penalty when doing garbage collection, he suggests. Itanic could be helped by a process shrink and wider issue width, by real vector (Cray-like) instructions, but most of all by compiler improvements. Vector machines have a bit of a bad reputation today, one that is, in my opinion unjustified. Yammer the Hammer No, he hasn't seen what he describes as "rumors" of Yamhill, Intel's own 64bit skunkworks project, but commends AMD's Hammer as a better approach. The memory interface is on the processor, and the traditional bus has been replaced by networks to communicate with the I/O. This allows glueless 4 way SMP setups, better I/O bandwidth, and better memory latency.