5/14 AMD announces mobile chips. Yay for competition.
\_ Whatever. x86 is for girls and kids, Real Men
use RISC!
\_ What do women use then?
\_ women don't use computers, they are barefoot and pregnant
and in the kitchen fetching men beers.
\_ Where's *my* barefoot, pregnant, beerfetcher?
\_ you've got to be capable of getting a woman pregnant
first. I hate beer. Mine's in there cooking and
cleaning.
\_ hehe, i make mine work, so I can stay home and
chill all day. =)
\_ Which corner of what city? I've got $5 burning
pure RISC or CISC chips but cam the stupid
a hole in my pocket and want to do something
nice for a homeless guy.
\_ Get out there and make me some money, bitch!
\_ Isn't it true that there's no such thing as true RISC or true
CISC anymore, that they're both converging?
\_ Yes. This knowledge makes it safe to ignore the kids who
think they're kewl because they use RISC chips and not a
recent x86 or clone which is basically a RISC chip.
\_ You're an idiot. x86 chips are not RISC (yes, I know
RISC/CISC is a stupid gradient and that there are no
pure RISC or CISC chips but can the stupid
technicalities) they have a CISC ISA. In this case,
it's because their instructions are non-orthogonal
and of variable width. They also have non-symmetric
pipeline orders which makes it difficult to employ
modern microprocessor techniques to speed up processors.
As a result, most modern day x86 processors employ a
decode stage microcode expansion to make it execute
much like what a RISC processor would. The goal of
the designers is to design a RISC-like chip but history
prevents them from straying away from their original
CISC ISA so they now have to implement this kludge
which works but is not very ideal. By the way,
those of you who still think that RISC means "few
instructions" while CISC means "many instructions"
are morons who don't read the book or pay attention
in class.
\_ So what does RISC and CISC mean now ?
\_ don't forget the 8 general registers instead of
an yother architecture's 32+ registers.
\_ The fact that x86 clones dumb down the RISC core speaks
volumes. Real men use RISC not RISC with CISC on top.
\_ but even RISC uses RISC with *ISC on top
\_ It's nice that you can babble out a bunch of stuff about
RISC/CISC in an effort to sound smart, but you really
should have stopped at the part about the gradient
between the two and that lack of true CISC or RISC chips
today. Then you might have sounded smart. But, no, you
just had to continue on and counter your own best point.
Where was I? Oh yes, you're an idiot.
\_ Oooh, you're so cool because you obviously have no
clue and are one of those loud-mouth morons who
just like to insult other people without having the
balls or the merits to back it up. "I'm cool because
I read the CISC/RISC article posted on Slashdot. I'm
technically competent because I work at a b2bi
startup doing ASP programming". You're a moron.
You're fucking clueless because you obviously didn't
even attempt to refute a single thing I said.Ã…
\_ You refuted it yourself just fine. I pointed that
out already. Thanks for making it so easy.
\_ real men fab their own chips, and run them on potatoes.
\_ real men don't use terminals either, they whistle 300 baud
tones down the telephone line.
\_ feh! real men program by yelling series of ones and zeroes
into the cable.
\_ Real men are somewhere else and not blathering about baud
rates and the CiSC/RISC gradient on the motd.
\_ like me! .... oh wait... |
http://csua.com/feed/