8/16    What exactly does VLIW try to depict?  Does it mean that (1) all
        instructions within an issue window are independent or (2) all
        instructions within an execution window are independent.  It seems
        that EPIC which claims to be VLIW more resembles #1 while most
        of the Phillips/TI DSP chips more closely resembles #2.
        \_ this is a SysAdm Farm, wrong place to ask this kinda question
        \_ what do you mean by "depict"? As I understand it, all instructions
           issued simultaneously execute simultaneously. Why would you put
           them in the same issue window if they had some kind of hazards
           between them?
           \_ Well, #2 is inclusive of number #1.  What I meant by #1 was
              that it was just the multiple instructions issued per cycle
              that were independent and not all the intructions in the
              pipeline.  For example, IA64 only restricts all 3 instructions
              in the 128 bit issue to be independent but that's just it.
              TMS320C67 and the Trimedia 1300 requires that all outstanding
              (non-committed) instructions be independent of all types of
              hazards.  Obviously #2 saves on a lot more hazard detection
              hardware but makes it nearly impossible to schedule code.
              But which is the actual definition of VLIW?
              \_  Asking what the actual definition of VLIW is like asking
                  what the actual definition of RISC is. It depends on who
                  you ask.