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| 5/24 |
| 2000/4/24-26 [Computer/HW/CPU] UID:18101 Activity:high |
4/24 http://www.techweb.com/wire/news/1997/10/1011merced.html \_ whatever happened to Merced? \_ Intel feared that the UC Regents would sue them for using this name which was reserved for the next UC Campus, UC Merced, so they renamed the chip to "Itanium". \_ Is this for real? (Having been away from campus for too long.) \_ Please. Merced is the name of a river as well as a city. It can't be reserved for UC. \_ Then is a "UC Merced" for real? \_ Yes, just search the UC web site for the details. \_ Merced and it's successors have been dubbed "Itanium"--and is shipping in engineering samples. Expect to see it comercially \_ this is a giant corp, though. Much like a student group, it makes progress on a purely geological timescale. some time this year. \_ Along with Iridium, they are planning to let it fall out of orbit and incinerate later this year. \_ "later this year" is what they said 2 years ago \_ this is a giant corp, though. Much like a student group, it makes progress on a purely geological timescale. \_ Um, no. Two years ago, folks expected Merced *design* to be finished in the same year (though no one at Intel thought that). Design finished last year, followed by actual silicon, followed by engineering samples. There are actual chips out now, as opposed to feel-good statements about when things will be done. \_ Unfortunately for Intel, rumor has it that the chip kind sucks and missed the boat as technology chip kinda sucks and missed the boat as technology marched on. We'll see when it gets here. \_ And of course, while Linux, IBM, HP, SCO & Sun will have Itanium-ready 64-bit OS'es this year, MS will make you wait for Windows 2002. \_ Oh ya? I thought they were already doing builds on it? \_ Well, Intel learned a lot on the Merced probject, and so though the first rev might not be terribly special, it is being used to finish the OSes on it. It's successor is being done faster because of that learning. Expect the successor to come out shortly (< 1.5-2 yeras) after Merced. |
| 5/24 |
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| www.techweb.com/wire/news/1997/10/1011merced.html Some experts believe will also open up a Pandora's box of technical challenges as it works to implement the instruction set in its upcoming 64-bit Merced microprocessor. Toughest will be extracting maximum performance from IA-64 while ensuring that Merced stays compatible with existing X86 software. In addition, Intel's engineers will face tight design constraints as they attempt to support numerous, complex IA-64 instructions while maintaining the shortest critical paths in silicon. To date, Intel has revealed almost nothing about IA-64 other than to trumpet it as the first "post-RISC" architecture. Moreover, Intel firmly insists it has not implemented a very-long-instruction-word (VLIW) approach--something that's been widely assumed. That sounds impressive, but to achieve it, a smart compiler must find enough parallelism in the applications software to dole out those eight instructions for execution. That's tough, since there are often tricky interdependencies between instructions and data; Like TI's C6X, most leading-edge architectures seek to take maximum advantage of parallelism. Still, Intel is going to great lengths to ensure that the term "VLIW" isn't used in conjunction with its new architecture. Interestingly, Joseph Fisher, the key architect at MultiFlow, is a member of the Hewlett-Packard Co. Gwennap sees IA-64 as taking advantage of VLIW concepts, but in a very different way from the pure VLIW approaches of a decade ago. These will include 64-bit analogs of the existing MMX instruction-set extensions, the next-generation MMX2 multimedia instructions coming to the 32-bit X86 architecture next year (see Sept. Intel is also equipping Merced with heavy-duty floating-point performance, the source close to Intel said. That's long been a perceived weakness of Intel chips as compared with their RISC competitors, and should enable Merced to stake a claim to computationally intensive applications in areas like scientific visualization and electronic-design automation. However, at least one Intel competitor thinks that IA-64 may be more sizzle than steak. Indeed, Intel has publicly stated that an imperative for Merced is "object-code compatibility," so that the new processor can execute the X86 instructions. Legacy conversion One tack--which Digital takes with its Alpha CPUs--is to use off--chip software-translation technology, converting old X86 code into the chip's native instruction set. The question is, are they going to impact the native IA-64 machine to ensure a higher degree of compatibility, or are they going to do it in software? Though noting that Intel has pledged compatibility, Gwennap of the Microprocessor Report, said the company won't address the subject in its IA-64 presentation this week. Chip architects aim to tighten up the members of their instruction set--and thus shorten their critical paths--as much as possible. However, the historical baggage of the Intel architecture may play a role in clock speed, an arena where Intel CPUs have played leapfrog with their RISC competitors--and often lost. Production versions of Intel's Pentium II top out at 300 MHz. This raises the question of why it doesn't have better clock speeds. There's also the issue of how much work you get done per clock cycle. Inherently, the IA-64 architecture is designed for increased parallelism, and thus more performance per clock cycle. So whether or not Intel can match Digital's clock speed isn't really the point. |