Berkeley CSUA MOTD:Entry 17911
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2025/04/03 [General] UID:1000 Activity:popular
4/3     

2000/4/2-3 [Computer/SW/Database, Computer/HW/Memory] UID:17911 Activity:high
4/1     EE question.  Why would the delay through a CAM (content addressed
        memory) cache, like those used in TLBs, increase with size. Since
        CAMs are built with each entry connected to a comprator and the
        selection is done through an N-way multiplexor using straight
        pass logic gates (no multiplexor select line decoding is involved)
        then theoretically a 64 entry CAM should be about as fast as a
        32 entry CAM right (at least it shouldn't be drastically slower)?
        \_ how much slower is a 64 entry CAM? if it's on the order of a few
           ns, then it's the additional stage required to select between the
           output of the decoders and routing. if it's larger, then your
           assumption that there's one decoder per entry is wrong.
           \_ But in this case there is no need to decode the select lines
              since the select lines are not in an encoded form.  They
              come from the actual comparators themeselves so there are
              N select lines for an N-entry CAM.  There is no time to
              decode the select lines.
              \_ i guess if each select line is an OE for a buffer which
                 drives the output pads, then yeah. I guess using tristate
                 buffers instead of muxes on the output is the right way of
                 doing this. so what's the answer? have you looked at a
                 datasheet?
                 \_ I actually don't know the answer. I don't think anyone
                    makes an entire IC as a CAM for them to publish a
                    datasheet for them.  But every prof I've had in
                    \_ MCM69C233, for example.  you must not have looked
                       really hard, since i found one at the first place
                       i bothered to check.
                    computer architecture related courses have always
                    said that larger TLB's and higher associativity caches
                    are slower.  I don't see why.
                    \_ bigger rams are slower.  larger area is slower than
                       smaller area.  i can get a big tag ram for a direct
                       mapped cache.  or i can split the tag ram in 2 and
                       do 2-way associativity.  each ram is smaller, but i
                       eat an extra couple of levels of logic to figure out
                       which way hits.  is one always faster than the other?
                       doubt it for small cache sizes/ways.  probably for
                       extreme cases the n-way cache is always slower.  ditto
                       for cams.  i can see for small sizes the difference in
                       loading/driving the pass gate wouldn't make much
                       difference if num loads go from 32 to 64.  can't do
                       pass gates for large loads.  for large cams the extra
                       levels of logic to decode the hit entry will make a
                       difference.
2025/04/03 [General] UID:1000 Activity:popular
4/3     

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