12/6 Is anyone speaking at the GM?
\_ Yes.
\_ 1'|| SP34|<, d00d! -B1FF
12/7(?) Can anyone point me to a good CISC vs. RISC article / paper? Thanx.
\_ Wasn't the consensus that the argument is meaningless?
Most chips today have the best qualities of both.
\_ No, most designers avoid CISC if at all possible. Intel chips
allow for their legacy CISC ISA to run on their modern
chips but that's just a hack (CISC instructions are decoded
into micro-RISC ops). Basically, many things will not work
unless what you execute are RISC instructions (pipelining,
Tomasulo dynamic execution, etc...). Intel chips suffer in
that all instructions must pass through one extra level of
decoding which could effect branch prediction recovery and
because variable length instructions can cross cache block
boundries instruction causing miss penalties and rates to go up.
\_ Patterson & Hennessey
\_ something like "A case for RISC" from Computer Architecture
News" by David Patterson (1980). There's also a very famous
dissertation from a Berkeley student. If you give me some
time I'll look it up.
\_ - D. Patterson & D. Ditzel, "The Case for the Reduce
Instruction Set Computer," Computer Architecture
News 8,6 (Oct 15, 1980)
- Manoils Katevenis, "Reduced Instruction Set
Computer Architecture for VLSI," PhD Dissertation,
EECS, UC Berkeley, 1982.
--jeff
\_ Are what they said still more or less valid, now that
it's been two decades and the industry has been moving
fast?
\_ kubi seemed to have recommended the reading to us.
he didn't recommend anything more recent but probably
because more recent work in architecture isn't
focused on ISA as much as it was in the 80's
--jeff
\_ "Why my x86 r00lz y0r powermac!!!11", Dudester69!11 |
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